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500 MHz Dual DCL ADATE206
FEATURES
Driver, comparator, and active load 500 MHz toggle rate Inhibit mode function Dynamic clamps Operating voltage range: -1.5 V to 6.5 V Output voltage swing: 200 mV to 8 V Four range adjustable slew rate True/complement data mode bit 100-lead TQFP package, exposed pad Low per channel power 1.4 W with load off 1.75 W with load programmed at 20 mA nominal Low leakage (<10 nA) in High-Z mode Driver 50 output resistance 1 ns minimum pulse width for a 3 V step Load: -35 mA to +35 mA maximum current range
7 69 8 68 9 67 6 70 22 54 23 53 24 52 25 51 26 50 27 49 28 48 29 47 15 61 14 62 10 65 11 66
FUNCTIONAL BLOCK DIAGRAM
VCC (18, 19, 57, 58, 77, 78, 89, 98, 99) NC (30, 46) SHIELDS (80, 82, 94, 96)
VIT VIL VIH
ADATE206
DR_INV DR_DATA_P DR_DATA_P_T DR_DATA_N_T DR_DATA_N DR_EN_P DR_EN_P_T DR_EN_N_T DR_EN_N VTEN LDEN
CLAMPL CLAMPH
LOGIC
DRIVER
81 95
DUT
APPLICATIONS
Automatic test equipment Semiconductor test systems Board test systems Instrumentation and characterization equipment
CVH COMP_H_P COMP_H_N CLLM COMP_L_P COMP_L_N
91 85 31 45 32 44 13 63 34 42 35 41 90 86
COMP_H
GENERAL DESCRIPTION
The ADATE206 is a complete, single-chip solution that performs the pin electronics functions of driver, comparator, and active load (DCL) for ATE applications. The active load can be powered down if not used. The driver is a proprietary design that features three active modes: data high mode, data low mode, and term mode, as well as an inhibit state. The driver has low leakage (<10 nA) in High-Z mode. The output voltage range is -1.5 V to +6.5 V to accommodate a wide variety of test devices. The ADATE206 supports four programmable Tr/Tf times for applications where slower edge rates are required. The edge rate selection is done via two static digital CMOS select bits. The input data to the driver can be inverted using a single CMOS logic bit. This feature can be used for system calibration or applications where complement input data is needed.
COMP_L
CVL
IOL LOAD LOGIC
VCOM
1 75
1x
VIOL VIOH GNDREF
4 72 3 73 2 74
IOH
TEMP SENSOR (5 DIODES)
88
TEMP
05738-001
VEE (16, 17, 33, 43, 59, 60, 84, 87, 92)
GND (5, 12, 20, 21, 36, 40, 55, 56, 64, 71, 76, 79, 83, 93, 97,100)
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
ADATE206 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Table of Contents .............................................................................. 2 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics............................................................. 3 Absolute Maximum Ratings ............................................................8 ESD Caution...................................................................................8 Pin Configuration and Function Descriptions..............................9 Typical Performace Characteristics ............................................. 12 Theory of Operation ...................................................................... 15 Outline Dimensions ....................................................................... 16 Ordering Guide .......................................................................... 16
REVISION HISTORY
1/06-- Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADATE206 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VCC = 10.0 V, VEE = -5.0 V, TJ = 75C, unless otherwise noted. Table 1.
Parameter DRIVER Single-Ended Logic Input Characteristics (VTEN, DRV_INV) Threshold Voltage Voltage Range Bias Current Single-Ended Logic Input Characteristics (SLEW0, SLEW1) Threshold Voltage Voltage Range Bias Current Bias Current Differential Logic Input Characteristics (DR_DATA_N, DR_DATA_P, DR_EN_N, DR_EN_P) Voltage Range Differential Voltage with LVPECL Levels Bias Current VIH, VIL Reference Inputs Input Bias Current VIT Reference Inputs Input Bias Current DC Output Characteristics Logic Range, VIL, VIH, VIT Amplitude [VH to VL] Output Resistance PSRR, Drive or Term Mode Static Current Limit Absolute Accuracy--VIH, VIL, VIT VIH Offset VIH Gain Error VIH Linearity Error Min Typ Max Unit Test Conditions/Comments
CMOS_VDD/2 0 -10 5.5 +10
V V A
VIN = 0 V, 3.3 V
CMOS_VDD/2 0 -10 +600 (@ 3.3 V) 1 5.5 +800
V V A mA
VIN = 0 V, 3.3 V VIN = 5.5 V
-2.0 250 -10 -10
+3.5 300 +2 -2 +10 +10
V mV A A
VIN = 3.24 V, 3.495 V Maximum value bias of reference sweep Maximum value bias of reference sweep
-25
+12
+25
A
-1.5 47.5 -125 10 110
+6.5 8 52.5 +125
V V mV/V mA
VCC, VEE 1% Output to -1.5 V, VH = 6.5 V, VT = 0 V Data = H, VH = 0 V, VL = -1.5 V, VT = 3 V Data = H, VH = 0 V to 5 V, VL = -1.5 V, VT = 3 V Data = VH relative to line between 0 V to 5 V; full range of VIH = -1.4 V to +6.5 V Data = L, VL = 0 V to 5 V, VH = 6.5 V, VT = 3 V Data = VH relative to line between 0 V to 5 V; full range of VIH = -1.4 V to +6.5 V Data = VT, VT = 0 V, VL = 0 V, VH = 3 V Data = VT, VT = 0 V to 5 V, VL = 0 V, VH = 3 V
-100 0.98 -15
+30
+100 1.02
mV V/V mV
+5
+15
VIL Offset VIL Gain Error VIL Linearity Error
-100 0.98 -15
+30
+100 1.02 +15
mV V/V mV
+5
VIT Offset VIT Gain Error
-100 0.98
+30
+100 1.02
mV V/V
Rev. 0 | Page 3 of 16
ADATE206
Parameter VIT Linearity Error Min -15 Typ +5 Max +15 Unit mV Test Conditions/Comments Data = VH relative to line between 0 V to 5 V; full range of VIH = -1.4 V to +6.5 V 65C to 105C VIH = 5.0 V; VIL = -1.5 V, +4.7 V, +4.8 V, +4.9 V VIH = 3.0 V; VIT = -1.5 V, +2.9 V, +3.1 V, +6.5 V VIL = 0.0 V; VIH = 0.1 V, 0.2 V, 0.3 V, 6.5 V VIL = 0.0 V; VIT = -1.5 V, -0.1 V, +0.1 V, +6.5 V VIT = 1.5 V, VIL = -1.0 V; VIH = -0.8 V, +1.4 V, +1.6 V, +6.5 V VIT = 1.5 V, VIH = 6.0 V; IL = -1.5 V, +1.4 V, +1.6 V, +5.8 V Terminated 20% to 80%, VIH = 400 mV, VIL = 0 V, VIT = 0 V Terminated 10% to 90%, VIH = 1.0 V, VIL = 0 V, VIT = 0 V Terminated 10% to 90%, VIH = 2.0 V, VIL = 0 V, VIT = 0 V Unterminated 10% to 90%, VIH = 3.0 V, VIL = 0 V, VIT = 0 V Terminated 20% to 80%, VIH = 3.0 V, VIL = 0 V, VIT = 0 V using DUT comparator Unterminated 10% to 90%, VIH = 5.0 V, VIL = 0 V, VIT = 0 V Terminated, VIH = 1.0 V, VIL = 0 V, VIT = 0 V Terminated, VIH = 3.0 V, VIL = 0 V, VIT = 0 V Unterminated, 50/50 dc measured frequency when amplitude drops 10% Terminated, VIH = 3.0 V, VIL = 0.0 V, VIT = 0.0 V Terminated, VIH = 3.0 V, VIL = 0.0 V, VIT = 0.0 V, 65C to 85C Terminated, VIH = 3.0 V, VIL = 0.0 V, VIT = 0.0 V, 1s period, pulse width = 50 ns to 1 ns Terminated, VIH = 3.0 V, VIL = 0.0 V, VIT = 0.0 V, 1 s period; 10%, 50%, and 90% duty cycle
Offset Tempco Driver Interaction VH Interaction to VL VH Interaction to VT VL Interaction to VH VL Interaction to VT VT Interaction to VH
80 -2 -2 -2 -2 -2 +2 +2 +2 +2 +2
V/C mV mV mV mV mV
VT Interaction to VL Rise/Fall Times at Device Under Testing (DUT) 0.2 V Swing: Rise/Fall Time 0.5 V Swing: Rise/Fall Time 1 V Swing: Rise/Fall Time 3 V Swing: Rise/Fall Time 3 V Swing: Rise/Fall Time
-2
+2
mV
300 350 500 650 350 450 550
ps ps ps ps ps
5 V Swing: Rise/Fall Time Minimum Pulse Width at DUT 500 mV Swing 1 1.5 V Swing1 Toggle Rate @ 3 V
1.1
ns
500 800 500
ps ps MHz
Dynamic Performance, Drive (VH and VL) Propagation Delay Time 2 Propagation Delay Tempco2
1.4 2.0
ns ps/C
Delay Matching, Edge-to-Edge Delay Change vs. Pulse Width2
20 30
ps ps
Delay Change vs. Duty Cycle2
5
ps
Rev. 0 | Page 4 of 16
ADATE206
Parameter Settling Time to 15 mV Settling Time to 4 mV Rise and Fall Time Temperature Coefficient 500 mV Swing Min Typ 8 32 Max Unit ns ns Test Conditions/Comments Terminated, VIH = 3 V, VIL = 0.0 V, VIT = 0.0 V Terminated, VIH = 3 V, VIL = 0.0 V, VIT = 0.0 V Terminated 10% to 90%, VIH = 1.0 V, VIL = 0.0 V, VIT = 0.0 V, 65C to 85C Terminated 10% to 90%, VIH = 2.0 V, VIL = 0.0 V, VIT = 0.0 V, 65C to 85C Unterminated 10% to 90%, VIH = 3.0 V, VIL = 0.0 V, VIT = 0.0 V, 65C to 85C Unterminated 10% to 90%, VIH = 5.0 V, VIL = 0.0 V, VIT = 0.0 V, 65C to 85C Terminated, VIH = 400 mV Terminated, VIH = 2 V Unterminated Unterminated Terminated, VIH = 3.0 V, VIL = -1.0 V VH = 3.0 V, VL = -1.0 V, terminated 50 Terminated, VIH = 3.0 V, VIL = -1.0 V Terminated, VIH = 3.0 V, VIL = -1.0 V Terminated, VIH = 0.0 V, VIL = 0.0 V, VIT = 0.0 V
2
ps/C
1 V Swing
2
ps/C
3 V Swing
2
ps/C
5 V Swing
2
ps/C
Overshoot and Preshoot 200 mV swing Overshoot and Preshoot 1 V swing Overshoot and Preshoot 3 V swing Overshoot and Preshoot 5 V swing Dynamic Performance, Inhibit Delay Time, Active High to Inhibit 3 Delay Time, Active Low to Inhibit3 Delay Time, Inhibit to Active High3 Delay Time, Inhibit to Active Low3 I/O Spike CLAMPS VCPH, VCPL Clamp Inputs VCPH Voltage Range VCPL Voltage Range Input Bias Current
1 1 2 2 3.1 2.1 2.5 3.9 350
% % % % ns ns ns ns mV
CLAMPL -1.8 -50
-2
6.8 CLAMPH +50
V V A
Maximum value bias of reference sweep = -1.8 V to +6.8 V Driver = INH, VCPH = 0 V Driver = INH, relative to line between 0 V to 4.5 V, VCPH = -1.5 V to +6.5 V, VCPL = -1.8 V Driver = INH, VCPL = 0 V Driver = INH, relative to line between 0 V to 4.5 V, VCPL = -1.5 V to +6.5 V, VCPH = 6.5 V
Absolute Accuracy VCPH, VCPL VCPH Offset VCPH Gain Error VCPH Linearity Error
-100
+55 1 +10
+100
mV V/V mV
VCPL Offset VCPL Gain Error VCPL Linearity Error
-100
+55 1 +10
+100
mV V/V mV
COMPARATOR DC SPECIFICATIONS 4 DC Input Characteristics (VOH, VOL) Bias Current Voltage Range Differential Voltage
-10 -1.5 -8.0
+5
+10 +6.5 +8.0
A V V
VOH and VOL = -1.5 V to +6.5 V
Rev. 0 | Page 5 of 16
ADATE206
Parameter Offset Gain Error Linearity Error Single-Ended Logic Input Characteristics Threshold Voltage (CLLM) Voltage Range Bias Current Bias Current Digital Output Characteristics (VOH, VOL Levels) Logic 1 Logic 0 Differential Levels COMPARATOR AC SPECIFICATIONS Propagation Delay Input to Output Propagation Delay Tempco Propagation Delay Change with Respect to PD vs. Duty Cycle Min -15 Typ 1 3 CMOS_VDD/2 0 -10 +160 260 5.5 +200 Max +15 Unit mV % FSR mV V V A A Test Conditions/Comments Common mode = 0 V VIN = -1.5 V to +6.5 V VIN = -1.5 V to +6.5 V
VIN = 0 V, 3.3 V VIN = 5.5 V
3.1 2.7 350
3.26 2.86 400
3.4 3.1 450
V V mV
Terminated 50 to 3.3 V Terminated 50 to 3.3 V Terminated 50 to 3.3 V
500 1.0 40
ps ps/C ps
VIN = 3 V p-p, 2 V/ns VIN = 3 V p-p, 2 V/ns VIN = 0 V to 3 V, 2 V/ns, driver in VTERM, VIT = 0 V, period = 10 ns; dc = 1 ns, 5 ns, 9 ns VIN = 0 V to 3 V, driver in VTERM, VIT = 0 V VIN = 0 V to 500 mV, 0 V to 1 V, 0 V to 3 V, 2 V/ns, driver in VTERM, VIT = 0 V VIN = 0 V to 1 V, <50 ps, 20% to 80% rise time, driver in VTERM = 0V VIN = 0 V to 3 V, 2 V/ns; pulse width = 3 ns, 4 ns, 5 ns, 10 ns; driver in VTERM, VIT = 0 V Settling to 8 mV, VIN = 0 V to 3 V, driver in VTERM, VIT = 0 V 2 V terminated, 1 V at the comparator, driver in VTERM, VIT = 0 V, 1 s period, pulse width = 50 ns to 1 ns VIN = 100 mV, sweep CVL and CVH HCOMP rise to LCOMP rise, HCOMP fall to LCOMP fall
Slew Rate: 1 V/ns, 2 V/ns, 3 V/ns Amplitude: 500 mV, 1.0 V, 3.0 V
30 30
ps ps
Equivalent Input Rise Time
225
ps
Pulse-Width Linearity
20
ps
Settling Time Minimum Pulse Width
5.5 1
ns ns
Hysteresis Comparator Propagation Delay Matching, HCOMP to LCOMP LOAD DC SPECIFICATIONS Single-Ended Logic Input Characteristics Threshold Voltage (LDEN) Voltage Range Bias Current Input Characteristics VIOL Current Program Range VIOH Current Program Range VIOH, VIOL Input Bias Current VDUT Range
6 50
mV ps
CMOS_VDD/2 0 -10 0.0 0.0 -10 -1.5 5.5 +10 3.5 3.5 +10 +6.5
V V A V V A V
VIN = 0 V, 3.3 V VDUT = -1.5 V, +6.5 V; IOL = 0 mA to 35 mA VDUT = -1.5 V, +6.5 V; IOH = 0 mA to 35 mA VIOL = 0 V, 3.5 V; VIOH = 0 V, 3.5 V |VDUT - VCOM| > 1.0 V
Rev. 0 | Page 6 of 16
ADATE206
Parameter VDUT Range VDUT Range Output characteristics Gain Load Offset, IOH, IOLT Load Nonlinearity, IOH, IOLT Min -1.5 -1.5 Typ Max +6.5 +6.5 Unit V V Test Conditions/Comments VDUT - VCOM > 1.0 V; IOH = 0 mA to 35 mA VCOM - VDUT > 1.0 V; IOL = 0 mA to 35 mA Slope of line between 5 mA and 30 mA IOH and IOL programmed at 20 mV (200 A) Relative to a line from 5 mA to 30 mA; IOL, IOH from 200 A to 35 mA Measured at IOH, IOL = 30 mA IOL, IOH = 20 mA, VCOM = 0 V VCOM = -1.5 V to +6.5 V IOL, IOH = 20 mA, VCOM = -1.5 V to +6.5 V IOL, IOH = 20 mA, VCOM = -1.5 V to +6.5 V, relative to a line at 0 V and 5 V VTT = 2 V, VCOM = 4 V/0 V, IOL = 20 mA, IOH = 20 mA VTT = 2 V, VCOM = 4 V/0 V, IOL = 20 mA, IOH = 20 mA Driver = INH, VDUT swept from -1.5 V to +6.5 V Driver = INH, VDUT swept from -1.5 V to +6.5 V
9.5 -200 -50
10
10.5 +200 +50
mA/V A A
Output Current Tempco, IOH, IOLT VCOM Buffer (Through Bridge) VCOM Buffer Offset VCOM Buffer Bias Current VCOM Buffer Gain VCOM Buffer Linearity Error
3 10 -10 0.99 -10 3 +1 1 +1 10 +10 1.01 +10
A/C mV A V/V mV
Dynamic Performance Propagation Delay--IMAX to INHIBIT INHIBIT to IMAX TOTAL FUNCTION Output Leakage Current Output Leakage Current, Low Leakage Mode Output Capacitance Power Supplies 5 Total Supply Range Positive Supply, VCC Negative Supply, VEE Positive Supply Current, VCC Negative Supply Current, VEE Total Power Dissipation Positive Supply Current Load Disabled, VCC Negative Supply Current Load Disabled, VEE Total Power Dissipation Temperature Sensor Gain Factor
1 2
2.3 2.3
ns ns
-1.5 -200
+0.28 +10 2
+1.5 +200
A nA pF
9.75 -5.25 190 240 2.5 145 190 1.8
10.0 -5.0 210 270 3.5 165 220 2.8 10
15.5 10.25 -4.75 245 300 4 200 250 3.3
V V V mA mA W mA mA W mV/C
Load enabled at 20 mA, driver is set to VIL = 0 V Load enabled at 20 mA, driver is set to VIL = 0 V Load enabled at 20 mA, driver is set to VIL = 0 V Load enabled at 0 mA, driver is set to VIL = 0 V Load enabled at 0 mA, driver is set to VIL = 0 V Load enabled at 0 mA, driver is set to VIL = 0 V Five diodes in series
1 s period, pulse width = 50 ns to 500 ps, pulse width measured when amplitude drops 10%. Measured at 50% of input amp to 50% of output amp. 3 tPD measured from the 50% of enable signal to 50% of output. 4 The low leakage mode of the comparator, controlled by VLLM input, reduces the leakage due to the comparator input. The comparator operates in this mode, but its bandwidth is compromised and is not guaranteed. 5 Under no circumstances should the input voltages exceed the supply voltages.
Rev. 0 | Page 7 of 16
ADATE206 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Maximum Current for VCC Maximum Current for VEE Positive Supply Voltage (VCC to GND) Negative Supply Voltage (VEE to GND) Operating Temperature (Junction) Storage Temperature Range ESD (Human Body Model) Rating 245 mA 300 mA +10.5 V -5.5 V +150C -65C to +150C 1500 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 8 of 16
ADATE206 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND/SHIELDS GND/SHIELDS GND/SHIELDS GND/SHIELDS
CVH_1
CVH_2
DUT_1
DUT_2
CVL_1
CVL_2
TEMP
GND
GND
GND
GND
GND
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
VCOM_1 GNDREF_1 VIOH_1 VIOL_1 GND D_INV_1 VIT_1 VIL_1 VIH_1
GND
VCC
VCC
VCC
VCC
VCC
VEE
VEE
VEE
1 2 3 4 5 6 7 8 9 PIN 1
75 74 73 72 71 70 69 68
VCOM_2 GNDREF_2 VIOH_2 VIOL_2 GND D_INV_2 VIT_2 VIL_2 VIH_2 CLAMPH_2 CLAMPL_2 GND CLLM_2 LDEN_2 VTEN_2 VEE VEE VCC VCC GND GND DR_DATA_P_2 DR_DATA_P_T_2 DR_DATA_N_T_2 DR_DATA_N_2
CLAMPL_1 10 CLAMPH_1 11 GND 12 CLLM_1 13 LDEN_1 14 VTEN_1 15 VEE 16 VEE 17 VCC 18 VCC 19 GND 20 GND 21 DR_DATA_P_1 22 DR_DATA_P_T_1 23 DR_DATA_N_T_1 24 DR_DATA_N_1 25
ADATE206
TOP VIEW (Not to Scale)
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
SLEW1
SLEW0
VEE
GND
GND
VEE
NC
COMP_L_P_1
COMP_L_N_1
COMP_H_P_1
COMP_L_N_2
COMP_L_P_2
CMOS_VDD
COMP_H_N_1
COMP_H_N_2
COMP_H_P_2
DR_EN_P_1
NC
DR_EN_P_T_1
DR_EN_N_T_1
DR_EN_N_T_2
DR_EN_P_T_2
DR_EN_N_1
DR_EN_N_2
DR_EN_P_2
Figure 2. Pin Configuration
Rev. 0 | Page 9 of 16
05738-002
ADATE206
Table 3. Pin Function Descriptions
Pin No. 1 2 3 4 5, 12, 20, 21, 36, 40, 55, 56, 64, 71, 76, 79, 83, 93, 97, 100 6 7 8 9 10 11 13 14 15 16, 17, 33, 43, 59, 60, 84, 87, 92 18 19, 57, 58, 77, 78, 89, 98, 99 22 23 24 25 26 Mnemonic VCOM_1 GNDREF_1 VIOH_1 VIOL_1 GND Description Commutation Reference Voltage. Reference GND for VIOL, VIOH. Program Voltage for IOH (Sink). Program Voltage for IOL (Source). Device Ground.
D_INV_1 VIT_1 VIL_1 VIH_1 CLAMPL_1 CLAMPH_1 CLLM_1 LDEN_1 VTEN_1 VEE VCC DR_DATA_P_1 DR_DATA_P_T_1 DR_DATA_N_T_1 DR_DATA_N_1 DR_EN_P_1
Driver Invert. Driver Term Voltage Reference. Driver Low Voltage Reference. Driver High Voltage Reference. Low Clamp. High Clamp. Comparator Low Leakage Mode. Determines Whether LD Responds to DR_EN_1 or is Disabled (see Table 4). Low Speed Control Signal. When high, DR_EN_1 forces driver output to VIT. Otherwise, DR_EN_1 forces driver to high impedance (see Table 4). Negative Power Supply. Positive Power Supply. High Speed Data Inputs. Sets high/low state of driver output (see Table 4). Termination Resistor for HS Inputs. Opposite end of each 50 termination resistor goes to the appropriate signal. Termination Resistors for HS Inputs. Opposite end of each 50 termination resistor goes to the appropriate signal. Complement of DR_DATA_P_1. High Speed Enable Inputs. Multifunction depending on status of VTEN_1 and LDEN_1. Causes driver to enter/leave inhibit; driver to enter/leave termination mode; load to leave/enter inhibit (see Table 4). Termination Resistor for HS Inputs. Opposite end of each 50 termination resistor goes to the appropriate signal. Termination Resistor for HS Inputs. Opposite end of each 50 termination resistor goes to the appropriate signal. Complement of DR_EN_P_1. No Connect. High Comparator Output. Complement of COMP_H_P_1. Low Comparator Output. Complement of COMP_L_P_1. Logic Signals Controlling Driver Slew Rates for Both Drivers. 00 codes for maximum slew voltage; 11 codes for minimum slew voltage. CMOS Supply (Internal / 2 = Single-Ended Logic Reference). Complement of COMP_L_P_1. Low Comparator Output. Complement of COMP_H_P_1. High Comparator Output.
27 28 29 30, 46 31 32 34 35 37, 39 38 41 42 44 45
DR_EN_P_T_1 DR_EN_N_T_1 DR_EN_N_1 NC COMP_H_P_1 COMP_H_N_1 COMP_L_P_1 COMP_L_N_1 SLEW1, SLEW0 CMOS_VDD COMP_L_N_2 COMP_L_P_2 COMP_H_N_2 COMP_H_P_2
Rev. 0 | Page 10 of 16
ADATE206
Pin No. 47 48 49 50 Mnemonic DR_EN_N_2 DR_EN_N_T_2 DR_EN_P_T_2 DR_EN_P_2 Description Complement of DR_EN_P_2. Complement of DR_EN_P_T_2. Termination Resistor for HS Inputs. Opposite end of each 50 termination resistor goes to the appropriate signal. High Speed Enable Input. Multifunction depending on status of VTEN_2 and LDEN_2. Causes driver to enter/leave inhibit; driver to enter/leave termination mode; load to leave/enter inhibit (see Table 4). Complement of DR_DATA_P_2. Complement of DR_DATA_P_T_2. Termination Resistor for HS Inputs. Opposite end of each 50 termination resistor goes to the appropriate signal. High Speed Data Input. Sets high/low state of driver output (see Table 4). Low Speed Control Signal. When high, DR_EN_2 forces driver output to VT; otherwise, DR_EN_2 forces driver to high impedance (see Table 4). Determines Whether LD Responds to DR_EN_2 or is Disabled (see Table 4). Comp Low Leakage Mode. Low Clamp. High Clamp. Driver High Voltage Reference. Driver Low Voltage Reference. Driver Term Voltage Reference. Driver Invert. Program Voltage for IOL (Source). Program Voltage for IOH (Sink). Reference GND for VIOL, VIOH. Commutation Reference Voltage. Device Ground or Pin Shield. Output/Input Pin. Window High Reference Level. Window Low Reference Level. Temperature Sense, Five Diode String, Reference to GND. Window Low Reference Level. Window High Reference Level. Output/Input Pin.
51 52 53 54 61 62 63 65 66 67 68 69 70 72 73 74 75 80, 82, 94, 96 81 85 86 88 90 91 95
DR_DATA_N_2 DR_DATA_N_T_2 DR_DATA_P_T_2 DR_DATA_P_2 VTEN_2 LDEN_2 CLLM_2 CLAMPL_2 CLAMPH_2 VIH_2 VIL_2 VIT_2 D_INV_2 VIOL_2 VIOH_2 GNDREF_2 VCOM_2 GND/SHIELDS DUT_2 CVH_2 CVL_2 TEMP CVL_1 CVH_1 DUT_1
Rev. 0 | Page 11 of 16
ADATE206 TYPICAL PERFORMACE CHARACTERISTICS
2400 2200 2000 VIH = 5V
5 4 3 DRIVER = VIH
1600
LINEARITY ERROR (mV)
1800
VIL = 0V TERMINATION = 50
2 1 0 -1 -2 -3 -4
200mV/DIV
1400 1200 1000 800 600 400 200 0 0 2 4 6 8
VIH = 3V
05738-003
-5 -6 -2 -1 0 1 2 3 4 5 6 7
10 2ns/DIV
12
14
16
18
VDUT (V)
Figure 3. Driver Large Signal Response
240 220 200 VIH = 500mV VIL = 0V TERMINATION = 50
6 5 4
Figure 6. Driver VIH Linearity vs. Output
DRIVER = VIL
160
LINEARITY ERROR (mV)
180
3 2 1 0 -1 -2 -3
20mV/DIV
140 120 100 80 60 40 20 0 0 2 4 6 8 10 2ns/DIV 12 14 16 18
05738-004
VIH = 200mV
-4 -5 -2 -1 0 1 2 3 4 5 6 7
VDUT (V)
Figure 4. Driver Small Signal Response
10 0 -10
Figure 7. Driver VIL Linearity vs. Output
8 6
TRAILING FALL EDGE
DRIVER = VTERM
-30
LINEARITY ERROR (mV)
-20
TRAILING RISE EDGE
4 2 0 -2 -4
05738-008
10ps/DIV
-40 -50 -60 -70 -80 -90 -100 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5
05738-005
-6 -8 -2
25.0
-1
0
1
2
3
4
5
6
7
2.5ns/DIV
VDUT (V)
Figure 5. Driver Trailing Edge Timing Error vs. Pulse Width
Figure 8. Driver VTERM Linearity vs. Output
Rev. 0 | Page 12 of 16
05738-007
VIH = 100mV
05738-006
VIH = 1V
ADATE206
1.0004 1.0003 1.0002 1.0001 1.0000 0.9999 0.9998 0.9997
05738-009
4.0 3.5 3.0
OFFSET (mV)
GAIN (V/V)
2.5 2.0 1.5 1.0
05738-012
0.9996 0.9995 60 70 80 90 100
0.5 0 -2
110
-1
0
1
2
3
4
5
6
7
TEMPERATURE (C)
COMMON-MODE VOLTAGE (V)
Figure 9. Driver Gain vs. Temperature
2.0 1.5 1.0
OFFSET (mV)
Figure 12. Comparator Offset vs. Common-Mode Voltage
1100 1050 1000 950 900 850 800 750 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 -50 -100
0.5 0 -0.5 -1.0 -1.5 60
50mV/DIV
05738-010
0
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
5500
6000
6500
8000
7500
8000
8500
9000 9000
70
80
90
100
110
TEMPERATURE (C)
500ps/DIV
Figure 10. Driver Offset vs. Temperature
Figure 13. Comparator Schmoo at 1 ns Rise and Fall Time
240 220 200 180 160
20mV/DIV
140 120 100 80 60 40 20 0 2 4 6 8 10 12 14 16 18 20
05738-011
0
500
1100 1050 1000 950 900 850 800 750 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 -50 -100
VIN = 0V TO 1V <50ps 20% TO 80% RISE TIME DRIVER IN VTERM = 0V
50mV/DIV
1000
1500
2000
2500
3000
3500
4000
4500
5000
5500
6000
6500
8000
7500
8000
8500
tBASE (2ns/DIV)
500ps/DIV
Figure 11. Comparator Differential Output Response
Figure 14. Comparator Schmoo at 600 ps Rise and Fall Time
Rev. 0 | Page 13 of 16
9500
05738-017
9500
05738-016
VIN = 0V TO 1V <50ps 20% TO 80% RISE TIME DRIVER IN VTERM = 0V
ADATE206
32.0 30.0 27.5 25.0 20.0 22.0 17.5 15.0 12.5 10.0 7.5 5.0
05738-018
18 16 14 VCOM = 0V IOL = 0V VDUT = 2V
LINEARITY ERROR (A)
12 10 8 6 4 2 0 -2 -4 0 5 10 15 20 25 30 35
05738-014
2.5ps/DIV
2.5 0 -3.0 1 2 3 4 5 1ns/DIV 6 7 8 9 10
IOL (mA)
Figure 15. Comparator tPD vs. Pulse Width
40 30 20 10 VCOM = 1V IOH = IOL = 35mA 14 12 10
Figure 17. Active Load Linearity vs. IOH
VCOM = 2V IOH = 0V VDUT = 0V
LINEARITY ERROR (A)
8 6 4 2 0 -2
IDUT (mA)
0 -10 -20
05738-013
-4 -6 0 5 10 15 20 25 30 35
-40 -2
-1
0
1
2
3
4
5
6
7
VDUT (V)
IOL (mA)
Figure 16. Active Load Commutation Region
Figure 18. Active Load Linearity vs. IOL
Rev. 0 | Page 14 of 16
05738-015
-30
ADATE206 THEORY OF OPERATION
The ADATE206 has two general classes of logic inputs: differential inputs for controlling functions that generally need to be operated at high speed, and single-ended CMOS inputs for setting operating modes or other low speed functions. The differential inputs have a wide common-mode range that allows them to be used with a variety of logic families. The differential inputs can be used single-ended, with one input from each pair of inputs tied to a fixed reference. However, this makes precise timing more difficult to achieve. These differential input pins provide 50 input termination resistors for use as desired. The single-ended inputs have an input range compatible with most logic families and are high impedance to make driving them very easy. The switching threshold for the single-ended inputs is preset to one-half of the voltage at the CMOS_VDD pin.
Table 4. Driver and Load Modes
LDEN (CMOS Single-Ended) 0 0 0 0 0 0 1 1 1 VTEN (CMOS Single-Ended) 0 0 0 1 1 1 0 0 0 DR_EN (High Speed Differential) 0 1 1 0 1 1 0 1 1 DR_DATA (High Speed Differential) X 0 1 X 0 1 X 0 1 Driver Status High-Z VIL VIH VIT VIL VIH High-Z VIL VIH Load Status High-Z High-Z High-Z High-Z High-Z High-Z ON High-Z High-Z
Table 5. Comparator Low Leakage Mode
CLLM (CMOS Single-Ended) 0 1 Typical DUT Pin Bias Current 1 A 10 nA
Table 6. Rise/Fall Time Selection 3 V, 10% to 90%, Unterminated
Slew1 0 0 1 1 Slew0 0 1 0 1 Tr/Tf (ns) 0.7 0.95 1.4 2.8
Table 7. Comparator Logic Function
DUT Pin Voltage >CVL >CVH >CVL CVH Rev. 0 | Page 15 of 16
ADATE206 OUTLINE DIMENSIONS
0.75 0.60 0.45 1.20 MAX
100 1 PIN 1
16.00 BSC SQ 14.00 BSC SQ
76 75 76 75 100 1
TOP VIEW
(PINS DOWN)
EXPOSED PAD
BOTTOM VIEW
(PINS UP)
1.05 1.00 0.95
0 MIN
0.15 0.05
SEATING PLANE
0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY
25 26
50 49
51 50 26
25
VIEW A
6.50 SQ
0.50 BSC LEAD PITCH
0.27 0.22 0.17
VIEW A
ROTATED 90 CCW
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD
Figure 19. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-100-2) Dimensions shown in millimeters
ORDERING GUIDE
Model ADATE206BSV Temperature Range -40C to +85C Package Description 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Package Option SV-100-2
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05738-0-1/06(0)
Rev. 0 | Page 16 of 16

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